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      "content": "well.. my boxes aren't configed for v6.  but I suspect I can dhcp6 or something",
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      "content": "@bunnie I am wiring up the CH347 to the NeTV2, will make a wiring diagram as part of making it work with Raspberry Pi 5, does the netv2 have an on board JTAG chip / programming port ? On the JTAG port attached to the Raspberry Pi is the RST pin equivalent of SRST on JTAG ?",
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      "content": "the ⁨`RES`⁩ pin next to GND goes to PROGRAM_B on the FPGA",
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      "content": "in other words, holding that low will fully reset the FPGA and cause it to reload its bitstream",
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      "content": "it's not a jtag reset",
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      "content": "it's a full system reset",
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      "content": "The IP address changes are needed due to changes in my networking.",
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      "content": "@bunnie - I notice the boards have that USB connector and chip, is that just a UART or could that be used to program things too? @Tisham Dhar (CSIRO EASI)  Does that USB exist on the 35t boards too?",
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      "content": "Yea the 35T has an FTDI chip and a USB connector, I was wondering if that was an on-board JTAG",
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      "content": "I haven't tested the CH347 with 35T yet. Was just confirming the wiring",
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      "content": "you mean the microUSB connector to the right of the HDMI connector? it's just a pair of FPGA pins brought out to a microUSB.",
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      "content": "i think the idea is that if you wanted to add e.g. a valentyUSB core to it you could do so",
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      "content": "I mean this one on the 35T",
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      "content": "Tried flashing the NeTV2 with my CH347T, no joy, raspberry pi does pick it up as a JTAG+UART, so that's a win. Could I please get a definitive wiring diagram from the CH347 to the NeTV2 JTAG port.",
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      "content": "The images above should have all the footprints and pinouts. My instinct on how JTAG wiring works seems off and the Captain DMA boards which using CH347 JTAG don't have open designs.",
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      "content": "@Tisham Dhar (CSIRO EASI) - I would expect that if OpenOCD is able to do things like read the FPGA ID and then program the SPI flashing gateware to write to the spi flash you have things connected correctly.",
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      "content": "@Tisham Dhar (CSIRO EASI) - It might also be worth trying with the Xilinx JTAG adapter first too.",
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      "content": "The programmer is not so much an issue as wiring it up correctly.",
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      "content": "The FPGA if fetched is not correct indicating I haven't mapped it nicely",
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      "content": "https://github.com/CarlFK/pici/wiki/ServerSetup  that image, you made the first version.  maybe that version. Any idea where the source is?",
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      "content": "@carlfk - That was a Google Drawing - I believe it is in the folder @ https://drive.google.com/drive/folders/103OYiqZFsTi16W23VrjE-Wm-A9bftEVj?usp=drive_link",
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      "content": "@carlfk - Doesn't look like that diagram ended up in that folder...",
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      "content": "agreeed. it was made long before fpgas.online was regeisted",
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      "content": "search your drive for \"Independent\" - and page though the 100 hits :p",
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      "content": "really this was to give you a starting point for explaing your IP address needs",
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      "content": "The GPIO for programming in that diagram is not feasible. I am trying to replace it with CH347 over USB",
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      "content": "@Tisham Dhar (CSIRO EASI) - I was really talking about all the other connections",
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      "content": "All other connections seem to work and should be part of the build.",
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      "content": "\\o/",
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      "content": "did you make the font smaler or something?  There seems to be more chars in the shell terminal",
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      "content": "@Tim 'mithro' Ansell now we get to play Why doesn't it boot?",
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      "content": "https://welland.fpgas.online/fpgas/pi25.html  the Pi did a dhcp request, evidance is the server responce:",
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      "content": "4:38:26 PM: dnsmasq: dhcp old b8:27:eb:47:9f:d1 10.31.0.125 pi25 rpi-47-9f-d1",
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      "content": "I'm ssh to tweed.  I can guess the setup, but a diagram might be nice",
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      "content": "@carlfk - I wouldn't touch tweed at the moment, I'm trying to get the AI to summarize the changes it made",
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      "content": "@Tim 'mithro' Ansell have it make digrams untill it matches how you connected the wires :p",
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      "content": "I'm a little affraid you have 2 dhcp servers on the same ... subnet?  lan?  whatever you don't want",
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      "content": "I think I have fixed that with vlans, but there are some complications.",
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      "content": "I think AI broke it beyond repair",
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      "content": "https://github.com/CarlFK/pici/blob/main/ansible/roles/pxe/templates/pibs.conf.j2",
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      "content": "# 4th IP octet = 100+index x.y.z.103",
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      "content": "dhcp-range=10.31.0.128,10.31.0.254,255.255.0.0,12h",
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      "content": "100 to 127 are ... I have no idea what happens.",
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      "content": "@carlfk - I'm going to rework my home network so that the fpgas and IPs stay at 10.31.X.X rather than having to move to 10.41.X.X which should reduce the curn in the pici ansible",
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      "content": "im still curious what you are trying to do",
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      "content": "Oh, wait it looks like pici uses 10.21.X.X ?",
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      "content": "correct",
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      "content": "I'm trying to fit an \"isolated network\" of the fpgas.online hardware into my home network which is also trying isolate the supermicro BMC/coreboot hardware, the IoT network, the guest network and such. The goal is to prevent accidental exposure of my servers to devices which random people can connect too.",
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      "content": "the PIs and everyting else on the same PoE switch?",
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      "content": "Internet --> ten64.welland.mithis.com (gateway machine) --> Random networking hardware --> tweed --> PoE switch --> RPis",
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      "content": "@carlfk - And unlike in the US, I only have one public static IPv4 address rather than a small number of them.",
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      "content": "I suspect it will be easier to put tweed in place of ten64",
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      "content": "but if you have figured out how to tunnel to tweed, good.",
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      "content": "@carlfk - I can't do that because I need ten64 for my home network. As I said, unlike in Sunnyvale where I could give tweed a public IPv4 address I can't do that here.",
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      "content": "I also have the problem that tweed and the fpgas are a *long* way away from the internet ingress point, so there is a bunch of networking equipment between the gateway and tweed.",
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      "content": "long = too long for a run of cat5?",
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      "content": "im not really sure what the real limit is",
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      "content": "is outgoing byte count something to wory about?",
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      "content": "the home page of videos are not scaled server side - I send the full res and the player is shurnk",
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      "content": "The site has 1Gbs down / 100Mbit up",
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      "content": "I think a cat6 cable might just reach but it'll be a while before I can run that cable.",
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      "content": "@Tim 'mithro' Ansell how easy can you hook up 2 TT boards (different runs) to anything I can ssh to.  tweed or a arty pi.  or whatever.  something I can text how to address differenrt boards",
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      "content": "the one board I have online can us /dev/serial/by-id/usb-MicroPython_Board_in_FS_mode_de640cb1d3975a26-if00",
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      "content": "I'm wondering how unique  de640cb1d3975a26",
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      "content": "@carlfk If you remind me on Wednesday, it should be pretty easy in theory.",
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      "content": "I\"m up at Monarto setting things for my parents until late tomorrow.",
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      "content": "@Tim 'mithro' Ansell I need help - I think git sub-modules is the answer.",
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      "content": "git submodules is an answer, it is rarely a good answer despite how much we use it \uD83D\uDE1B",
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      "content": "to boot Kianv o tt6, I need this stuff https://github.com/CarlFK/tt-commander-app/blob/feature/cli_bl910/src/ttcontrol/cli/boot_kianv_ulinux.sh",
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      "content": "part of the problem is the Arty fpga thing expanded to TT, and kinda just the 1 Kianv thing",
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      "content": "@carlfk - My plan is that when @Matt Venn and friends finish the TT FPGA emulation board, then we will have a bunch of those in the pool.",
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      "content": "@carlfk - I'm not game to do the vlan rename to fix the IP address stuff while I'm remote \uD83D\uDE1B",
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      "content": "@Tim 'mithro' Ansell im still stuck on how to get little_term.py on or close to the rp2040",
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      "content": "`little_term.py` meaning `litex_term.py` or?",
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      "content": "https://github.com/CarlFK/tt-commander-app/blob/feature/cli_bl910/src/ttcontrol/cli/little_term.py",
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          "description": "Web app to control the Tiny Tapeout Demo board. Contribute to CarlFK/tt-commander-app development by creating an account on GitHub.",
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      "content": "your ssh client -network- Pi -usb serial- RP2040 -uart serial- TT06 / 910 (KianV Linux)",
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      "content": "little_term.py runs on RP2040 to connect  Pi -usb serial- to -uart serial- TT06",
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      "content": "`mpremote fs cp little_term.py :` is the final step to install it, but none of the steps are automated.",
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      "content": "I'm trying to make it part of https://github.com/CarlFK/pici/wiki/Install",
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      "content": "@carlfk - I think your text diagram is a little bit hard to understand?\n\nIs this what you mean?\n`<something> <-????-> ssh client <- network -> RPi <- usb serial -> RP2040 <- UART serial -> TT06 Chip (Running 910 - KianV Linux)`",
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      "content": "BTW I have been learning about conserver which seems to be a tool for sharing serial ports over the network and supports things like multiple connections, logging the output and such.....",
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      "content": "I've recently started getting it working with the BMC serial over lan ports and also the USB-serial adapter on a RPi Zero which is connected to the consoles on my netgear network switches",
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      "content": "yes - as long as you understand what little_term.py does",
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      "content": "What is BMC serial?",
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      "content": "BMC == Board Management Controller -- it's a little Linux computer that is found on server motherboards which allows you to remotely access things like the power buttons, virtual vga screen, virtual serial port, etc....",
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      "content": "ok - I undersatnd BMC - how does serial fit in?",
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      "content": "The BMC lets you connect to the computer's serial port so you can see things like very early BIOS messages or if the linux running on the system is configured correctly even a console. Provides a way to get access to the machine when SSH isn't working or similar. I wanted computers like tweed to output dmesg messages to their serial port and log them so I could see things like kernal panics and such, hence why I was looking at conserver.\n\nBut it seems like conserver could be useful for just generally providing remote access to usb serial ports in an RPi as it deals with the problem of multiple devices trying to access the serial port at once (IE you could be connected with something like cu at the same time you connect little_term and another python script)....",
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      "content": "I'm skeptical :p - the only time I have that problem is when I forget I alreaday have something conected.",
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      "content": "for early dmesg messages - do you know about https://www.kernel.org/doc/Documentation/networking/netconsole.txt",
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      "content": "pass a kernel parameter append ... netconsole=@192.156.1.5/eth0,@192.168.1.3/00:08:02:a0\uD83C\uDD8Ecf",
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      "content": "very early it smashes that ip config and starts spewing udp",
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      "content": "I did in the past but had forgotten about that....",
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      "content": "I https://github.com/CarlFK/pici/blob/main/ansible/roles/fixpi/files/boot/ncc.py",
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      "content": "that beeps when it recieves, which is often when the box is crashing",
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      "content": "Fpga boards are now in the tt shop",
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      "content": "Now there are less FPGA boards in your shop \uD83D\uDE42",
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      "content": "@carlfk - I setup a couple more of the Tiny Tapeout boards on RPis here for you",
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      "content": "@carlfk - But I had the realisation this morning that I was doing the vlans slightly wrong",
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      "content": "I'm not sure what to do wiht this",
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      "content": "a diagram of what you have done would probably help",
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      "content": "@carlfk - Don't worry about it, give me about an hour and I should have it all fixed up",
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      "content": "@carlfk - Basically, the connection between ten64 (the gateway) and tweed's uplink port should be a *different* vlan to tweed's local port and the RPis so I end up with:\n\n  [tfpgas.ten64] <-- tfpga vlan on switches --> [eth-uplink.tweed : eth-local.tweed] <-- fpga vlan on S3300-1 --> [RPis]",
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      "content": "S3300-1 is a switch?",
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      "content": "Yes.",
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      "content": "A picture would answer these questions",
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      "content": "is  \"tfpga vlan on switches\" include the - \":fpga vlan on S3300-1\"  ?",
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      "content": "the PoE control code can and does have \"turn off all the PoE on all the ports\" which might brick the thing until pull the power cord and maybe poke the reset hole",
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      "content": "there is /etc/environment ... pi_ports=\"2 3 5 7 9 11 13 21 23 \"  which is only the ports in ansible inventory but thats only good/valid for what is stable, not experimenting with new things, like adding a TT setup to the fpga/arty setup",
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      "content": "also in /etc/environment  is `SNMP_SWITCH_AUTHKEY=` which I think needs an export for `source /etc/environment`  but adding export to that file will break EnvironmentFile=/etc/environment",
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      "content": "I could use some help with that.",
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      "content": "@Tisham Dhar (CSIRO EASI) - I was able to program the NeTV2 FPGA on a RPi5 using the GPIO headers.",
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      "content": "OpeOCD linuxgpiod driver ?",
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      "content": "@Tisham Dhar (CSIRO EASI) - Initially I was using OpenOCD with the gpiod driver (which was quite slow but still worked), but it looks like Claude has managed to create a new driver using the PIO found in the RP1 chip which is faster than the original broadcom bitbanging driver - https://github.com/mithro/rp1-jtag",
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      "content": "There is no drivers openOCD, push that to git and I will have a go with the NeTV2 I have here",
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      "content": "@Tisham Dhar (CSIRO EASI) - Did you do that write up building LiteX firmware for the NeTV2 anywhere?",
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      "content": "Install LiteX following the standard setup, then:\n\ncd litex-boards/litex_boards/targets\n\n# Build for XC7A35T variant with Ethernet\n./kosagi_netv2.py --variant=a7-35 --with-ethernet --build\n\n# Or for the 100T variant with PCIe\n./kosagi_netv2.py --variant=a7-100 --with-pcie --build\nThe target supports:\n\nDDR3 SDRAM: Using the K4B2G1646F module with LiteDRAM\nEthernet: RMII PHY via LiteEth\nPCIe: x4 Gen2 via LitePCIe\nSD Card: Both SPI mode and native SDIO\nLED Chaser: For the obligatory blinky demo",
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      "content": "@Tim 'mithro' Ansell  if you have a 35T then the bitstream is at the bottom of this page : https://github.com/ufrisk/pcileech-fpga/blob/master/NeTV2/readme.md",
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      "content": "Complete with code snippets : https://whatnicklife.blogspot.com/2026/01/loading-fpga-bitstreams-with-openocd.html?m=0",
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          "description": "A Hot Adelaide Afternoon and a Pile of FPGAs  I was recruited to wire together the NeTV2 to the Raspberry Pi 5 PCI bus by some means. Tim  d...",
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      "content": "@RebelMike - According to Claude you have done a bunch of work with the RP1 in the RPi5",
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      "content": "I did some stuff trying to hack it when it first came out",
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      "content": "There's piolib now though so you don't need to find an exploit just to use the PIOs \uD83D\uDE05",
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      "content": "@RebelMike - I have a crazy idea of having the RPi5 emulate larger (IE megabyte sized) spiflash/psram with the PIO for use both with Tiny Tapeout and BMC motherboard development -- kinda of a more advanced version of your emulation on the RP2040. \n\nIt looks like originally it was quite hard to get >10 Megabyte/second transfers between the RPi5 and PIO device but it looks like ~20->40 Megabyte/seconds might be possible now.\n\n * https://github.com/mithro/rp1-jtag\n * https://github.com/mithro/rpi5-rp1-pio-bench",
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          "description": "High-speed JTAG via Raspberry Pi 5 RP1 PIO. Contribute to mithro/rp1-jtag development by creating an account on GitHub.",
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      "content": "@Tisham Dhar (CSIRO EASI) - I should have debs and static versions of openFPGAloader with the rpi1-jtag support being built now",
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      "content": "I'm not sure what kind of latency you'd manage to get given there is PCIe in the middle ...",
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      "content": "I suspect getting deterministic performance over the PCIe bus would be tricky. I would have thought a RP2350 with PSRAM attached (maybe to GPIO instead of through XIP) would be preferable",
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      "content": "Although at that point why not just actually attach the PSRAM to the project. I guess you could support slightly different protocols, although never at a high clock speed",
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      "content": "One thing I think Pi 5 could be great at that I haven’t seen (though I haven’t looked recently) is a cheap logic analyser. PIO should be able to sample pins at 200MHz and you have reasonably fast access to GBs of memory",
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      "content": "@RebelMike / @tnt - I'll see what claude is able to do here if I put some hardware in the loop and let it iterate.",
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      "content": "I ***also*** have the crazy idea of using the RP1 PIO to do a C code LUNA type stack where you can to USB1/USB1.1/UTMI/ULPI on the GPIO pins.",
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      "content": "I don't think the USB idea would be very useful but it might be fun to try anyway....",
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      "content": "For USB there's https://github.com/sekigon-gonnoc/Pico-PIO-USB which only needs one PIO so might work - probably mainly depends on whether there's any latency issues.",
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      "content": "As far as I'm aware there's no facility for running code on the RP1's spare ARM core - but when it became clear Raspberry Pi weren't realy interested in making it possible for the community to do stuff in this area I kind of lost interest in it so I don't know about any more recent work",
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      "content": "@RebelMike - It appears that cleverca22 has been doing your logic analyser stuff https://github.com/cleverca22/libsigrok/commit/e3783bac8176e7454863b37723ab6d8a3f99731a",
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      "content": "Cool!",
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      "content": "How about using an FPGA for that?",
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      "content": "@urish - You mean like spispy? \uD83D\uDE1B",
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      "content": "I think so",
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      "content": "That is what I'm planning on using at the moment",
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      "content": "@clever helped me with fpga.online pi net boot",
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      "content": "which lead to https://kicanvas.org/?github=https%3A%2F%2Fgithub.com%2FCarlFK%2Fpimo%2Ftree%2Fmain%2Fproject",
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      "content": "@carlfk - I was going to tell you to invite @clever to this channel but it turns out he is already here!",
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      "content": "@carlfk - I think the corporate world would call this \"synergy\" \uD83D\uDE1B",
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      "content": "@Tim 'mithro' Ansell  rpi-pio-jtag talking to NeTV2 35T ->",
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      "content": "OpenFPGALoader is patched and built , however it is saying empty on detect",
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      "content": "Never mind , setting pins makes it work",
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      "content": "Making a PR",
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      "content": "k8s@node10:~/openFPGALoader $  cd /home/k8s/openFPGALoader && sudo ./build/openFPGALoader -c rp1pio --detect 2>&1\nempty\nrp1pio: using default pins TCK=4 TMS=17 TDI=27 TDO=22\nindex 0:\n        idcode 0x362d093\n        manufacturer xilinx\n        family artix a7 35t\n        model  xc7a35\n        irlength 6",
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      "content": "Lemme know if you are working on the OpenOCD implementation. I have Copilot hopping on that. I cannot test it under lspci yet since I dont have a power supply.",
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